1. Field of the Invention
The present invention relates to a high voltage semiconductor device and related manufacturing process. More particularly the invention relates to a power integrated device with vertical current flow.
2. Discussion of the Related Art
A very common problem in power integrated devices lies in the existence of parasitic effects due to the undesired interaction among the elements of the integrated circuit and the power transistor. In fact these devices are integrated on the same silicon substrate and are insulated from each other by junctions polarized in reverse-bias. Therefore the formation of parasitic components is inevitable with the realization of the power device. This power device can induce, above all during its switching on/off, some large disturbances on the circuit components connected thereto. The disturbances increase as the switching speed increases and as the voltage or current that the power device operates with increases. These disturbances are more considerable in the case of power integrated devices with vertical current flow.
The state of the art provides for the utilization of several technologies for the reduction or the elimination, where it is possible, of the parasitic components which are present in the power integrated device. These technologies provide for a substantial change in the structure of the power integrated circuits by introducing a dielectric layer, most often an oxide layer, to insulate the components.
For the insulation of the components of the power integrated devices with lateral current flow, several technologies are known, such as LOCOS and trench, and a technology providing for the utilization of buried oxide, otherwise called SOI. That technology is moreover used for the insulation of the power integrated devices with vertical current flow. The xe2x80x9cSOIxe2x80x9d technology however lends itself to different methods of implementation.
One of the methods more used is the so-called xe2x80x9cdielectric isolationxe2x80x9d. This method, used for power integrated devices with lateral current flow, requires supplementary manufacturing process steps. Starting with a silicon substrate, trenches are realized with oblique walls, by a selective etching of the silicon. Then the silicon surface is oxidized and a thick layer of polysilicon is deposited thereon. Then the silicon layer of the starting substrate is mechanically removed in order to arrive at the bottom of the trenches previously excavated. At the end silicon isles are obtained, totally enclosed by oxide, where it is possible to make the circuit components. The silicon layer serves only as a mechanical support and, in order to avoid to deposit very thick polysilicon layers, it is possible, as a variant of this method, to solder the silicon wafer thus obtained with another silicon substrate which, together with the polysilicon layer, serves as a mechanical support.
Another realization method of the xe2x80x9cSOIxe2x80x9d technology is xe2x80x9cSDBxe2x80x9d (Silicon Direct Bonding). This method, used for a power integrated device with lateral current flow, consists in the use of two silicon wafers that are firstly oxidized and then soldered. One of the two silicon wafers is thinned and polished. The other silicon wafer, of a given thickness, serves as a mechanical support. Therefore a single silicon wafer is obtained made up of a thin silicon layer superimposed on an oxide layer of given thickness, deriving from the union of the oxide layers of the two starting wafers, which is superimposed on a silicon layer of a given thickness. The circuits components will be realized in the thinned silicon layer. The realization of the lateral insulation of the integrated device is obtained by providing trenches in the silicon, which are deep to arrive to the buried oxide layer, and are filled up with suitable dielectrics, for example thermal oxide with a silicon nitride.
The xe2x80x9cSDBxe2x80x9d method, described before, can also be used for the realization of power integrated circuits with vertical current flow. After the soldering of the two silicon wafers is executed, and one of the two wafers is reduced to the desired thickness, a photolithography is executed in order to remove the silicon and the deposited oxide, in some regions of the device. The epitaxial growth of the doped silicon is executed and the doped silicon layer is planarized. So some xe2x80x9cislesxe2x80x9d of buried oxide are obtained wherein the low voltage components of the integrated device are obtained, such as those of signal or control, while the power component is made in the regions wherein the oxide is absent. The lateral insulation of the device is executed by realizing trenches in the silicon, deep enough to arrive at the buried oxide layer, and filled up with suitable dielectrics, for example thermal oxide with nitride.
A variant to the method above described for the realization of the power device with vertical current flow, provides, differently from the method above described, for the realization of the oxide isles, by photolithographic process, before of the soldering of the two wafers.
Another method used for the realization of the power device with vertical current flow, is xe2x80x9cSIMOXxe2x80x9d (Separation by IMplanted OXygen). This method consists in implanting oxygen ions with very high doses (1017-1018 ions/cm2) into the doped silicon wafer through a suitable photolithography mask. The implanted oxygen layer, after opportune thermal processes, reacts with the silicon forming silicon oxide in the region previously implanted. If the implant energy is adequately high, over the layer of silicon oxide a thin crystalline silicon layer remains, sufficient in order to realize the low voltage components, while in the region of the device wherein the silicon oxide is not present, the power component with vertical current flow can be realized.
However the methods before described for the realization of the power devices, have notable disadvantages. In fact the xe2x80x9cdielectric isolationxe2x80x9d method, due to the presence of the oblique walls, does not allow the reduction of the components sizes beyond some point. The xe2x80x9cSDBxe2x80x9d method, used for the realization of the power integrated circuits with vertical current flow, presents a notable complexity of realization. The process of wafer soldering, the epitaxial growth of the doped silicon and the successive implanting are very expensive processes. Also the epitaxial growth of the doped silicon in the region wherein the oxide layer is faced laterally to the surface, will produce defective silicon zones. The variant to the xe2x80x9cSDBxe2x80x9d method for the realization of the power device with vertical current flow, above described, presents a practical difficulty. In fact the soldering of the wafers whose surface is not uniform, in particular surfaces which present silicon zones alternated to silicon oxide zones, is more problematic and gives a lower yield. The xe2x80x9cSIMOXxe2x80x9d method for the realization of the power device with vertical current flow, is very expensive for the very high doses of the oxygen implant. The silicon layer over the oxide presents a number of defects which are particularly deleterious for the realization of the bipolar components. It is also possible that in the outline region of the buried oxide isle, defects are originated which propagate in the surrounding silicon, for the different coefficient of thermal expansion of the two materials.
In view of the state of the art described, it is an object of the present invention to provide a power integrated device with vertical current flow wherein the disturbances produced by switching of the power transistor are substantially reduced, and representing a more effective, simpler and less expensive solution than the present power devices.
According to the present invention, this and other objects are attained by an integrated circuit comprising a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer by an insulating material layer, wherein said power component with vertical current flow is formed in the second semiconductor layer, and excavations are formed in the insulating material layer which extend from a free surface of the first semiconductor layer to the second semiconductor layer, said excavations having lateral walls of insulating material and being filled up with a conductor material in order to electrically contact active regions of the power component in the second semiconductor layer by electrodes placed on the free surface of the first semiconductor layer.
As a result of the present invention it is possible to realize a power integrated device with vertical current flow wherein the disturbances produced by the switching of the power transistor are significantly reduced, allowing a three-dimensional integration of the device, not requiring an elimination of the buried insulated material layer for the manufacturing of the high voltage component, simpler to fabricate than the described manufacturing methods, not needing additional process steps such as an epitaxial growth of the silicon layer or the planarization of the silicon wafer, lowering manufacturing costs of the device, allowing a notable reduction of the sizes of the device.